1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and particularly to technology for controlling the formation of impurity-doped regions in a semiconductor layer by a method of working a gate electrode of the device by dry etching. The invention can for example be applied to displays wherein this semiconductor device is used in a display part, and particularly to liquid crystal displays, organic EL displays (a light emitting device or a light emitting diode) and electronic equipment using such displays. The EL (electroluminescent) devices referred to in this specification include triplet-based light emission devices and/or singlet-based light emission devices, for example.
2. Description of the Related Art
When in the fabrication of a semiconductor device a semiconductor layer is formed by dry etching or wet etching, or when an impurity region is formed in a semiconductor layer by doping, a mask made of photoresist is used.
In dry etching or wet etching, the material outside the part covered by the mask is removed, and the material which is not etched assumes the same shape as the shape of the mask. When doping is carried out, an impurity region is formed in the part of the semiconductor layer which is not covered by the mask.
In recent years, the microminiaturization of structures of semiconductor devices having thin film transistors (hereinafter, TFTs) has been progressing. Consequently, there has been a need for finer positioning in mask formation. Insufficiently fine positioning is a cause of formation defects in the forming of resist masks. There has been known a method whereby to overcome this a semiconductor device is fabricated by a part of a TFT (for example the gate electrode) being formed by dry etching and then other parts of the TFT (for example source and drain regions) being formed using this already-formed part of the TFT (for example the gate electrode) as a mask, self-aligningly.
With such a method for making a semiconductor device self-aligningly it is possible to realize a reduction in the number of photo masks used in the forming of photoresist masks by photolithography, and fine positioning is unnecessary. Because of this, the technology is currently receiving attention.
For the forming of an impurity region in a semiconductor layer, the method of doping the semiconductor layer with a group 15 (of the periodic table) impurity element such as phosphorus or arsenic or a group 13 (of the periodic table) impurity element such as boron is used.
Doping a semiconductor layer with a group 15 impurity element forms an n-type region, and doping with a group 13 impurity element forms a p-type region, and in this way source and drain regions are formed in a semiconductor layer.
A characteristic of a TFT is its OFF current (the current which flows through the channel region when the TFT is OFF; in this specification, Ioff). When the characteristics of a TFT are being evaluated, it is desirable that the value of this Ioff be small.
To make Ioff small, it is beneficial to form an LDD (Lightly Doped Drain) region in the part of the semiconductor layer positioned outside the gate electrode.
Also, if hot carriers arise in the channel region when the TFT is being driven (i.e. is ON), this causes the semiconductor device to deteriorate. To prevent this, it is desirable that a second LDD region be formed in a part of the semiconductor layer overlapping with the gate electrode.
A semiconductor device structure having an LDD region overlapping with the gate electrode across a gate insulating film is known as a GOLD (Gate-drain Overlapped LDD) structure.
GOLD structures are also called LATID (Large-tilt-angle implanted drain) structures and ITLDD (Inverse TLDD) structures. For example in xe2x80x98Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97 TECHNICAL DIGEST, P523-526, 1997xe2x80x99 it is confirmed that a GOLD structure with a silicon side wall provides extremely good reliability compared to other TFT structures.
In the fabrication of a semiconductor device having a TFT, the forming of a mask from photoresist necessitates many steps beforehand and afterward. These include for example substrate washing; the application of resist material; pre-baking; exposing; developing; and post-baking.
And the photoresist mask must be removed after the etching or doping process, and numerous steps are also required for this removal. These include for example ashing with a gas selected from among O2, H2O and CF4; removal using chemicals; or removal by means of a combination of ashing and chemical treatment. At this time, removal using chemicals necessitates steps such as chemical treatment; rinsing with pure water; and drying of the substrate.
Thus there has been the problem that using masks made from photoresist increases the number of steps required to make a semiconductor device.
And, along with the microminiaturization of semiconductor devices, finer positioning in mask formation has been required. Insufficiently fine positioning is a cause of formation defects of resist masks, as mentioned above, and time spent repairing such defects results in increased process time and has been a cause of increased manufacturing costs.
The use of masks made from photoresist in the fabrication of semiconductor devices has thus increased the number of steps required for the fabrication process; increased the time required to complete the steps; increased manufacturing costs; and affected product yield.
Accordingly, reducing the number of masks used is an effective way of reducing the manufacturing cost of a semiconductor device.
Also, when the characteristics of a TFT in a semiconductor device are considered, it is desirable that a first LDD region of the kind mentioned above be formed in the semiconductor layer, as this is effective in reducing Ioff which is an important characteristic of a TFT.
And to prevent deterioration of the semiconductor device it is preferable for the device to have a GOLD structure, and by forming a second LDD region of the kind described above so as to overlap with the gate electrode across the gate insulating film it is possible to suppress hot carriers forming in the channel region and the drain region.
In this specification document the above-mentioned first LDD region will be called the Loff region and the above-mentioned second LDD region will be called the Lov region.
However, to dope the Loff region and the Lov region with an impurity it has been necessary in each case to form a mask made of photoresist on the semiconductor layer, and the increase in the number of steps resulting from the increase in the number of masks needed has been a problem.
And, in a semiconductor device having a GOLD structure wherein the edge of the gate electrode is positioned on the gate insulating film above the boundary between the Loff region and the Lov region, fine positioning is necessary in the formation of the photoresist masks, and the process has been complicated. Consequently, trouble has often arisen which causes positioning failure at the time of mask formation.
For these reasons, in the forming of a semiconductor device having a, GOLD structure, because the structure necessitates fine positioning control, increased numbers of masks and trouble in the formation of photoresist masks have been a great problem and have constituted a cause of increased manufacturing cost of the semiconductor device, increased time required for manufacture, and reduced manufacturing yield.
To overcome this, the present inventors, having been researching the possibility of forming an Loff region and an Lov region to constitute LDD regions of a semiconductor device having a GOLD structure self-aligningly without using masks made from photoresist, have invented a fabrication method for forming an Loff region and an Lov region by doping a semiconductor layer with an impurity element self-aligningly by means of certain gate electrode materials and dry etching methods.
By using this invention it is possible to form an Loff region and an Lov region by doping the semiconductor layer with an impurity element self-aligningly and thereby to reduce the number of masks required and eliminate trouble associated with the formation of these masks. Thus it is possible to reduce the manufacturing cost of a semiconductor device and the time required for its manufacture.
In the fabrication of a semiconductor device, it is preferable to provide an LDD region. And to suppress deterioration of the semiconductor device, it is desirable to form a GOLD structure. However, to form an LDD region it has hitherto been necessary to form a mask made of photoresist. Consequently, increased mask numbers and increased manufacturing cost have been a problem. However, with the present invention it is possible to form an Loff region and an Lov region self-aligningly and thereby to reduce the number of masks needed to manufacture a semiconductor device and to reduce manufacturing time and manufacturing cost.
The edge of a gate electrode in a semiconductor device with a GOLD structure overlaps with part of the LDD region across the gate insulating film. In this invention the shape of the gate electrode is worked to a tapering shape, and doping is carried out self-aligningly a number of times using the gate electrode so worked as a mask. In this way, a source region, a drain region, an Loff region and an Lov region are formed. In the doping, by an impurity being doped through part of the gate electrode, the Lov region is formed in a part of the semiconductor layer overlapping with the gate electrode; consequently, impurity regions each having a different impurity concentration are formed in the semiconductor layer.
Specifically, the invention provides a method for forming a semiconductor device with a GOLD structure self-aligningly by means of a semiconductor device fabrication method including: a first step of forming a semiconductor layer; a second step of forming a gate insulating film on the semiconductor layer; a third step of forming a first conducting film on the gate insulating film; a fourth step of forming a second conducting film on the first conducting film; a fifth step of forming a gate electrode of a first shape by carrying out dry etching at least once on the second conducting film and the first conducting film; a sixth step of forming a first impurity region in the semiconductor layer; a seventh step of forming a gate electrode of a second shape by carrying out dry etching on the gate electrode of the first shape; an eighth step of forming a gate electrode of a third shape by carrying out dry etching selectively on the second conducting film of the gate electrode of the second shape; and a ninth step of forming a second impurity region in the semiconductor layer.
In this invention, for each of the first conducting film and the second conducting film a material is selected from among the refractory metals tungsten, tantalum, titanium, and molybdenum; nitrides having at least one of these metals as a main constituent; and alloys containing at least one of these metals. The first conducting film and the second conducting film are made of different materials.
A high-density plasma is used for the dry etching, and an etching apparatus is used with which it is possible to control independently the power of a plasma source and a bias power for generating a negative bias voltage on the substrate side. From experimental results obtained by the inventors it was discovered that the taper angle of the gate electrode edge depends on the bias voltage on the substrate side, and it was found that by setting the bias power of the dry etching apparatus higher it is possible to reduce the taper angle of the gate electrode. By suitably controlling the bias power it is possible to form a gate electrode having at its edge a taper angle of 5 to 80xc2x0, and this gate electrode is used as a mask for forming impurity regions.
In this specification document, for convenience, the angle that a sloping side face of a conducting layer makes with the horizontal will be called the taper angle; a sloping side face having this taper angle will be called a tapering shape; and a part having the tapering shape will be called the tapering part.
In the fifth step dry etching is carried out so that a taper angle of 5 to 60xc2x0 is formed on the edge of the gate electrode, to form a gate electrode of a first shape.
In the seventh step dry etching is carried out with a smaller bias power than in the fifth step. As a result of the bias power being made smaller, the taper angle of the gate electrode edge becomes larger than in the gate electrode of the first shape. Consequently, a gate electrode of a second shape, narrower in width than the gate electrode of the first shape, is formed.
In the eighth step the second conducting film is dry etched selectively. And in this step the taper angle of the edge of the second conducting film of the gate electrode of the second shape becomes larger. However, in the eighth step, because first conducting film of the gate electrode is hardly etched at all, a gate electrode of a third shape wherein the width of the second conducting film is narrower than that of the first conducting film is formed.
For forming the impurity regions, ion doping is used. Besides ion doping, ion injection can alternatively be used. In this invention when doping of the impurity is carried out a mask made from photoresist is not used and instead the gate electrode is used as a mask. Consequently the number of masks needed to make the semiconductor device is reduced. If an n-type semiconductor device is to be made, in the sixth step and the ninth step a group 15 impurity element such as phosphorus or arsenic is doped, whereas if a p-type semiconductor device is to be formed a group 13 impurity element such as boron is doped in the sixth step and the ninth step.
In the sixth step the impurity element is doped through the gate insulating film using the gate electrode of the first shape as a mask, and thereby a first impurity region is formed in the part of the semiconductor layer positioned outside the first shape. This first impurity region is a source or drain region.
In the ninth step a second impurity region is formed by the impurity element being doped using as a mask just the second conducting film of the third shape gate electrode. In the doping conditions in the ninth step a smaller dose and a higher accelerating voltage than in the conditions at the time of the formation of the first impurity region are used, so that a second impurity region having a lower impurity concentration than the first impurity region is formed in the semiconductor layer. And the impurity element is doped into the semiconductor layer through the first conducting film of the gate electrode of the third shape and through the gate insulating film. Of the second impurity region, an Loff region is formed outside the gate electrode of the third shape and an Lov region is formed in a region not overlapping with the second conducting film but overlapping with the first conducting film.
By using the above means a GOLD structure semiconductor device is formed which has a semiconductor layer including a source region, a drain region, an LDD region positioned outside the gate electrode and an LDD region overlapping with the gate electrode; a gate insulating film; and a gate electrode. Just two photo masks are needed to form this semiconductor device: a photo mask for forming an island-shaped semiconductor layer; and a photo mask for forming the gate electrode. After the gate electrode is formed using a mask, the source and drain regions and the Loft region and the Lov region are formed in the semiconductor layer self-aligningly.
By reducing the number of masks using the means described above it is possible to reduce the number of manufacturing steps and the time needed to produce the semiconductor device; reduce manufacturing cost; and improve yield.
It is also possible to form a GOLD structure in a semiconductor device having an island-shaped semiconductor layer, a gate insulating film and a gate electrode by processes besides that described above, with the same number of masks, by changing the process order and the conditions of the dry etchings and impurity dopings. Below, a specific manufacturing process constituting an example other than that set forth above is described.
That is, the invention also provides a method for forming a GOLD structure self-aligningly by means of a semiconductor device fabrication method including: a first step of forming a semiconductor layer; a second step of forming a gate insulating film on the semiconductor layer; a third step of forming a first conducting film on the gate insulating film; a fourth step of forming a second conducting film on the first conducting film; a fifth step of forming a gate electrode of a first shape by carrying out dry etching at least once on the second conducting film and the first conducting film; a sixth step of forming a first impurity region in the semiconductor layer; a seventh step of forming a gate electrode of a second shape by carrying out dry etching selectively on the second conducting film of the gate electrode of the first shape, an eighth step of forming a second impurity region in the semiconductor layer; and a ninth step of forming a gate electrode of a third shape by carrying out dry etching selectively on the first conducting film in the gate electrode of the second shape.
In this method, for each of the first conducting film and the second conducting film a material is selected from among the refractory metals tungsten, tantalum, titanium, and molybdenum; nitrides having at least one of these metals as a main constituent; and alloys containing at least one of these metals. The first conducting film and the second conducting film are made of different materials.
For the dry etching, an etching apparatus is used with which it is possible to control independently the power of a plasma source and a bias power for generating a negative bias voltage on the substrate side, or a parallel flat plate type RIE apparatus.
In the fifth step dry etching is carried out so that a taper angle of 5 to 60xc2x0 is formed on the edge of the gate electrode, to form a gate electrode of a first shape.
In the seventh step the second conducting film in the gate electrode of the first shape is etched selectively. Also, dry etching is carried out with a smaller bias power than in the dry etching of the fifth step. As a result of the bias power being made smaller, the taper angle of the second conducting film edge becomes larger than in the gate electrode of the first shape. And because the first conducting film is hardly etched at all, a gate electrode of a second shape wherein the width of the second conducting film is narrower than that of the first conducting film is formed.
For forming the impurity regions, ion doping is used. Besides ion doping, ion injection can alternatively be used. In the sixth step the gate electrode of the first shape is used as a mask, and a first impurity region is formed in the semiconductor layer positioned outside the first shape by an impurity element being doped through the gate insulating film. This first impurity region becomes a source or drain region.
In the eighth step a second impurity region is formed by doping the semiconductor layer with an impurity element using the second conducting film of the gate electrode of the second shape as a mask. In the doping conditions in the eighth step, a smaller dose and a higher accelerating voltage than in the conditions at the time of the formation of the first impurity region are used, so that a second impurity region having a lower impurity concentration than the first impurity region is formed in the semiconductor layer. And the impurity element is doped into the semiconductor layer through the first conducting film of the gate electrode of the second shape and through the gate insulating film.
In the ninth step, the first conducting film is dry etched selectively. In the first conducting film, because an extremely small taper angle is formed in the part not overlapping with the second conducting film as a result of the seventh step, the first conducting film is etched from its edge and narrows, and a gate electrode of a third shape is formed. At this time, a second impurity region has been formed in the semiconductor layer overlapping with the first conducting film, and as a result of the first conducting film becoming narrow a part of the second impurity region comes to be positioned outside the gate electrode of the third shape. Of this second impurity region, the region positioned outside the gate electrode of the third shape becomes an Loff region and the region overlapping with the gate electrode of the third shape becomes an Lov region.
Also by using the means described above, with two photo masks it is possible to form a semiconductor device having a semiconductor layer including a source region, a drain region, an Loff region and an Lov region; a gate insulating film; and a gate electrode.
The invention can be said to have a characterizing feature in the method by which the gate electrode is formed.
That is, the invention further provides a method for manufacturing a semiconductor device including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, the method including: a first step of forming a semiconductor layer on an insulating surface; a second step of forming an insulating film on the semiconductor layer; and a third step of forming on the insulating film a gate electrode made up of a first conducting layer and a second conducting layer having at its edge a taper angle larger than a taper angle at the edge of the first conducting layer.
In this method, the edge of the semiconductor layer is preferably given a tapering shape as shown in FIGS. 3A through 3E and FIGS. 9A through 9E.
And in this method, the edge of the first conducting layer preferably has a tapering shape, and to obtain this tapering shape, in the third step, the gate electrode is formed by carrying out dry etching using a chlorine-based gas and a fluorine-based gas or a chlorine-based gas and a fluorine-based gas and O2 and then carrying out dry etching using a chlorine-based gas and a fluorine-based gas and O2.
Because the second conducting layer has at its edge a larger taper angle (45xc2x0 to 80xc2x0) than the taper angle at the edge of the first conducting layer (below 60xc2x0 and preferably less than 5xc2x0), the second conducting layer is narrower in width than the first conducting layer.
The chlorine-based gas is a gas selected from among Cl2, BCL3, SiCl4 and CCl4. The fluorine-based gas is a gas selected from among CF4, SF6 and NF3.
A semiconductor device having a gate electrode having a tapering shape obtained by this method is also a characterizing feature of the present invention. It is possible to obtain a GOLD structure TFT self-aligningly by forming a gate electrode made up of a first conducting layer and a second conducting layer with differing taper angles and then carrying out doping of an impurity element.
That is, the invention further provides a method for manufacturing a semiconductor device including a semiconductor layer formed on an insulating surface, an insulating film formed on the semiconductor layer, and a gate electrode formed on the insulating film, in which method the gate electrode has a layered structure made up of a first conducting layer constituting a lower layer and a second conducting layer constituting an upper layer and having at its edge a taper angle larger than a taper angle at the edge of the first conducting layer and the semiconductor layer has a channel-forming region overlapping with the second conducting layer across the insulating film, an LDD region overlapping with the first conducting layer across the insulating film, and a source region and a drain region.
In this method, the edge of the semiconductor layer is preferably given a tapering shape as shown in FIGS. 3A through 3E and FIGS. 9A through 9E.
And in this method, as shown in FIGS. 3A through 3E and FIGS. 9A through 9E, the edge of the semiconductor layer is covered by an insulating film provided between the gate electrode and the semiconductor layer. And as shown in FIGS. 3A through 3E and FIGS. 9A through 9E, the insulating film has a tapering shape in the proximity of the gate electrode.